2 days old

Senior Staff ASIC Design Engineer

San Jose, CA
  • Job Code
Job Title: Senior Staff ASIC Design Engineer 155147

Primary Location United States-California-San Jose
Job: Design Engineering
Schedule: Full-time

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


Job Description
Xilinx is seeking an experienced front end implementation engineer for the development of high-performance IP blocks in the company’s next generation product.  Successful candidates will be responsible for prototype implementation of assigned IP blocks to ensure RTL meets all defined quality metrics.  As a member of the Hard IP Design group, you will work on both design flow automation and product implementation for tape-out.   Close interaction with both the RTL design team and signoff/back-end implementation team is essential.  Responsibilities include SDC generation/verification, logic synthesis, running RTL LINT, DFT DRC, and CDC verification.  Additional responsibilities may include the development of power intent constraints (UPF), running LEC, Memory BIST insertion, and scan insertion.  Maximizing efficiency through the effective use of automation throughout these processes is expected.


Job Requirements

Applicants should possess a BS/MS in EE or equivalent field with applicable work experience in the several of the following tools. The position requires substantial TCL-based scripting competence within CAD tool shell environments as well as stand-alone TCL shell scripts. Prior work experience in CAD, RTL, or front end implementation teams is expected.
  • Synopsys Design Compiler
  • Prime Time experience including SDC constraint development for complex blocks with many clock domains
  • Strong TCL scripting background
Experience in the following is highly desired:
  • Mentor Questa CDC (Zero In)
  • Fishtail  
  • Cadence Conformal LEC
  • Cadence Conformal Low Power including UPF development
  • Mentor Tessent Shell Memory BIST
Education and Years of Experience Requirements: Minimum of a BS with 12 years or MS with 8 years or PhD with 5 years
Education/Field Requirements: Electrical Engineering, Computer Engineering or related equivalent
Highly motivated candidates with strong written and verbal communication skills and structured, well-organized work habits are desired.

Job Posting: Apr 12, 2018, 7:46:06 AM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.


Posted: 2018-12-13 Expires: 2019-01-12

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Senior Staff ASIC Design Engineer

San Jose, CA

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