2 days old
2018-05-242018-06-23

Senior Staff Design Engineer

Xilinx
  • Job Code
    153622
Job Title: Senior Staff Design Engineer 153622

Primary Location India-India-Hyderabad
Job: Design Engineering
Schedule: Full-time
Description
  1. 10 years of experience in SoC/IP RTL design/SoC Integration
  2. Expertise in Protocols like SD Host 3.0/4.0, Gigabot Ethernet, low speed peripherals(I2C, SPI, UART etc)
  3. Work experience in ARM CPU based SOC system is required
  4. Good AXI based system and AXI bus knowledge is must have
  5. Must have synthesis and STA constraints experience for at least 1 SoC
  6. Should have knowledge in clock domain crossing (CDC), Linting and fishtail constraint analyzer knowledge
  7. Team player with ability to work with multisite and local teams
  8. Should have ASIC/SOC design flow competency
  9. Should be able to own SoC level tasks for system/subsystem IPs
  10. Need Excellent communication skill and sound debugging skills  


Qualifications
Education Requirements : BTec/MTech

Years of Experience: 10 years 
Job Posting: Apr 2, 2018, 4:28:52 AM


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Xilinx

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