11 hours

Senior Product Management Engineer - FPGA Implementation Software

San Jose, CA
  • Job Code
Job Title: Senior Product Management Engineer - FPGA Implementation Software 155645

Primary Location United States-California-San Jose
Job: Applications Engineering
Schedule: Full-time
Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


The Product Management Engineer position is in the FPGA Implementation Software group, located in San Jose (California), for an experienced engineer to focus on tools specification, validation, documentation and key customers support. The successful candidate will work closely with both the R&D team and tier-1 customers on specific issues to improve Vivado implementation software quality of results and ease of use. Daily activities will include the following:

  • Actively exploring innovative methodologies and their impact on flow and design practices.
  • Deep-diving on new and critical tool issues seen by customers to identify work-arounds and future enhancements.
  • Creating and tracking product development schedules and issues, and managing internal software development, as well as cross-functional projects with hardware, marketing and field support teams.
  • Interfacing with Senior Management, Quality, Tech Marketing and Application teams to ensure issues are resolved and corrective actions completed.
  • Developing and delivering training materials on new features and methodologies.
  • Authoring high quality documentation tuned to the needs of the reader for their areas of expertise
  • Staying current with and proposing the internal use of industry approaches, algorithms, and practices #hot

Education and Experience Requirements 

BS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 2 years of relevant experience.

  • Customer Awareness: Has good working knowledge of RTL-based design flows and expectations.

  • Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with in-depth expertise in timing analysis and closure. Has expertise in: HDL, Tcl, Timing and Physical Constraints (SDC/XDC), synthesis/placement/routing/verification tools.
  • Design Enablement: Expert in design analysis, experimentation and methodology for timing closure and runtime reduction.
  • Problem Solving: Ability to handle and solve complex system level issues, internally and with tier-1 customers.
  • Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear.

Job Posting: Jul 17, 2018, 11:37:31 AM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.


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Senior Product Management Engineer - FPGA Implementation Software

San Jose, CA

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