14 hours

Senior FPGA Timing Characterization Engineer

San Jose, CA
  • Job Code
Job Title: Senior FPGA Timing Characterization Engineer 155307

Primary Location United States-California-San Jose
Job: Design Engineering
Schedule: Full-time

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 

  • Responsible for developing methodologies to simulate and/or run STA Tools to capture FPGA Timing.
  • Design, implementation, test, integration and delivery of system level digital designs for FPGA blocks timing verification
  • Apply STA of concepts and related tools to generate, debug and validate timing models and correlate timing values to silicon measurements.
  • Need to lead projects for single chip and stacked silicon full chip timing model validation and characterization and Tuning of Timing files.
  • Provide project schedule estimates, progress updates and technical risk identification
  • Develop design specifications based on project requirements
  • Need to maintain an effective communication with local and remote teams
  • Ensure to complete design and timing verification tasks within allotted timeline

  • Bachelors or Masters in Electronics engineering with 8 to 12 years of experience in Digital Design or Silicon characterization
  • Should be knowledgeable about all the internal blocks of FPGA like DSP, BRAM, I/O etc
  • Good understanding of device technology, custom circuit and digital designs and electrical analysis
  • Strong scripting skills using Perl, Python, C-shell or similar scripting languages.
  • Experience with Xilinx FPGA design/ implementation tools a plus
  • Good analytical, communication, presentation and troubleshooting skills are required

Job Posting: May 10, 2018, 1:02:32 PM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.


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Senior FPGA Timing Characterization Engineer

San Jose, CA

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