4 days old
2018-07-112018-08-10

Senior Engineer RTL Design

Xilinx
San Jose, CA
  • Job Code
    155476
Job Title: Senior Engineer RTL Design 155476

Primary Location United States-California-San Jose
Job: Engineering Services
Schedule: Full-time
Description
Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, programmable SoCs and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable adaptable, intelligent computing.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative and creative people to help deliver groundbreaking technologies that build an adaptable intelligent world. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.

 


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As a member of the FPGA Silicon Design Full Chip RTL team, you'll be responsible for development of RTL models for synthesized and custom logic. Using formal verification tools to prove the RTL models are accurate to the transistor model. Use power models to describe the power intent of the model. Verify the clock domain crossings are correctly designed. Help develop and prove new RTL methodologies.

 

Responsibilities will include but are not limited to

  • Exercises solid analytical problem solving and troubleshooting skills (e.g., LEC debugging, Functional simulation debugging, Script debugging )
  • Model the power profile of a design and use power reduction techniques on the design.
  • Run LEC on synthesized designs at several places in the design cycle, Pre DFT,Post DFT, Post Layout, ECO
  • Coordinate with tool vendors to resolve tool issues, make test cases to show issue.
  • Mentor less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones
  • Strong scripting and automation using Perl, Python, TCL, Make and/or other scripting languages



Qualifications

Education Requirements

  • Master’s degree in Electrical Engineering or related field. 

Years of Experience

  • 4 years of progressive experience as IC Design Engineer, CPU/ GPU/ FPGA Hardware Engineer, ASIC RTL Design  or related occupation 

Alternative Requirement:          

  • Bachelor’s degree in Electrical Engineering or related field plus six (6) years of progressive experience as IC  Design Engineer, CPU/ GPU/ FPGA Hardware Engineer, ASIC RTL Design or related occupation

Experience Required:   

·         Exceptionally strong System Verilog coding skills.

·         Experience synthesizing RTL with Design compiler or Verific

·         Experience running formal verification with Conformal or Formality.

·         Experience in RTL functional simulation, Writing simple test benches, using Verdi to debug behavior.

·         Nice to have : UPF power modeling, ESP verification, Verific coding skills. 


Job Posting: Jun 19, 2018, 4:43:43 PM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.

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Senior Engineer RTL Design

Xilinx
San Jose, CA

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San Jose, CA

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