12 hours
2018-05-242018-06-23

Senior CAD Engineer.

Xilinx
San Jose, CA
  • Job Code
    154930
Job Title: Senior CAD Engineer. 154930

Primary Location United States-California-San Jose
Job: CAD/Layout
Schedule: Full-time
Description
Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.

 

Job Description:

 

 

 

Xilinx is looking for a person to join the CAD Organization to define and develop innovative methodologies for transistor-level timing closure and
gate-level path delay estimation. As part of the CAD team, you will have the chance to drive new flow development and take a leading role in
pushing our next generation technologies to silicon.

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Responsibilities
  • Responsible for CAD flow ownership/support for Transistor-level STA (Static Timing Analysis) flow
  • Responsible for CAD flow ownership/support for Gate-level path delay estimation flow
  • Work with cross-functional teams to write new flow/methodology specification, implement to those specification, and develop test plans and regressions
  • Development and documentation of procedures, guidelines, and best practices
  • Work with EDA vendors on implementing solutions for new design challenges

 



Qualifications
Technical Competencies
  • Strong understanding of scripting languages including Perl/Csh/Tcl
  • Strong understanding of complex data structures and object-oriented programming
  • Strong understanding of data exchange formats including Verilog, SPICE, SPEF, and DSPF
  • Experience with industry standard STA tools PrimeTime and NanoTime
  • Experience with SPICE simulation using HSPICE and/or other simulators
  • Experience with Virtuoso for data import/export is a plus
  • Experience with revision control concepts and tools such as Perforce and IC Manage is a plus
  • Experience with flow automation tools such as FlowTracer or Lynx to implement complex, multi-step flows is a plus

Job Posting: Mar 13, 2018, 11:08:58 PM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.

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Senior CAD Engineer.

Xilinx
San Jose, CA

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San Jose, CA

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