2 days old

Staff Hardware Development Engineer

San Jose, CA
  • Job Code
Job Title: Staff Hardware Development Engineer 154548

Primary Location United States-California-San Jose
Job: Design Engineering
Schedule: Full-time

Job Description:

Xilinx is seeking a talented, motivated and self-driven FPGA engineer to be part of the SDAccel platform IP development team. SDAccel is the next generation software programming environment under the SDx initiative to enable application developers with little or no FPGA expertise to use high level programming languages such as OpenCL, C and C to leverage the power of programmable hardware for application acceleration.


This high performance team is involved in development of a scalable, reconfigurable acceleration platform that can be optimized for machine learning, video transcoding, image and speech recognition, CloudRAN, and Big Data analytics applications. Candidate will get an opportunity to work on deployment of FPGAs with Tier1 hyperscale cloud as well as other customers.



  • End-to-end system level design of the platform including hardware, board, shell design development. Responsibilities will also include integration of hardware, firmware and software and making sure they all work together.
  • FPGA IP integration and testing, board and system hardware bring up of the shell used in acceleration applications in FPGA based PCIe cards
  • Xilinx FPGA design, synthesis, speed and gate optimization, Verilog code development, test bench creation and validation of the design
  • Hands-on work involving board bring-up, debugging and validating designs that use PCIe Gen3/4, high speed Ethernet networking, DDR3/ DDR4, AXI interconnect and other networking protocols.
  • Define the requirements by working with software and firmware teams to implement complete system level solution
  • Drive the planning, implementation, architecture and microarchitecture and verification of acceleration platform features.



Qualifications & Skills:

  • FPGA design tool flows, synthesis, timing analysis, partitioning, FPGA programming, bring up and testing
  • Knowledge of timing constraints like Synopsys Design Constraints format.
  • Extensive past experience in FPGA IP integration and testing, board and system hardware bring
  • Knowledge of networking protocols, interfaces and standards like PCIe Gen3/4 and 10G Ethernet
  • Knowledge of memory interfaces like DDR3, DDR4
  • Knowledge of AXI interconnect protocol
  • Knowledge of serial protocols like I2C, SPI, JTAG
  • Scripting with Tcl, which is the application programming interface for Vivado, and Perl/Python
  • Team working skills
  • Analytical skills
  • Good communication and interpersonal skills
Preferred Skills and Experience:
  • Basic knowledge of C, Linux environment
  • Experience with Xilinx tools
  • Experience with high level synthesis and working knowledge of OpenCL


  • MS/PhD in Electrical Engineering and minimum 5 years relevant work experience Bachelor’s degree in Electrical Engineering and 8 years relevant work experience.

Job Posting: Dec 18, 2017, 2:40:28 PM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.


  • Engineering

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