2 days old

Staff Design Engineer

  • Job Code
Job Title: Staff Design Engineer 154345

Primary Location India-India-Hyderabad
Job: Design Engineering
Schedule: Full-time
Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

Candidate should be have in-depth knowledge of the Verilog. He should have done RTL design for SRAM blocks, FIFO, Error correcting codes, interconnect.

As a senior design engineer he should be able to lead the RTL and verification effort for the team. Good communication skill is required  interacting peers with cross site as well.

Job Requirement :

BS with 10   years in Electrical Engineering, Computer Engineering, or Computer Science. Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques and experience with FPGA programming and software is a plus.

Should have good aptitude and analytical and problem solving skills.

Knowledge of SRAM and interconnect is a plus.

Job Posting: Nov 20, 2017, 2:21:07 AM


  • Engineering

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