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Senior Staff Physical Design/Timing Lead

San Jose, CA
  • Job Code
Job Title: Senior Staff Physical Design/Timing Lead 154870

Primary Location United States-California-San Jose
Job: Design Engineering
Schedule: Full-time

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs.

We are looking for an individual to join the Communication and MAC IP COE group as a Senior Staff Design Engineer, leading the Physical Design and Timing function within our team.

As a Physical Design and Timing Lead, you will be responsible in leading the team in completing all the back end related deliverables for each of the Communication IP blocks.  You will work cross functionally with other teams in resolving technical issues with synthesis, routing, amongst others as the blocks are quite complex, and in improving the methodology in handoffs between the different teams.  You are motivated to learn the features of the Communication IP blocks.  You are an expert in the back end tools and understand the ASIC design flow. 


  • Manage the back end deliverables for each of the Communication IP block
  • Develop and implement plans to synthesize, implement including Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block level (100K to 1M gates) which are coded in VHDL/Verilog
  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements
  • Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule
  • Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements
  • Lead the team as the technical advisor and mentor other engineers
  • Document all the back end deliverables #jm



  • Bachelor's Degree in Electrical or Computer Engineering; MS Preferred
  • 15  years of experience in design flow from Netlist to GDS, Floor Plan, Synthesis, Route, STA, CTS, RC Extraction and correlation
  • Demonstated experience in static timing analysis, power and noise analysis and back-end verification across multiple projects
  • Proficient with backend design EDA tools Synopsys (preferred) or Cadence
  • Experienced in Design-For-Test tools & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation)
  • Experience with Verilog or VHDL and Digital Design Principles
  • Successfully track records of taping out complex SOC in 16nm and beyond
  • Working knowledge of deep sub-micron routing issues as they relate to power and timing
  • Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing analysis
  • Self-motivated team worker, good verbal and written communication skills
  • Knowledge with LINT and CDC tools
  • Strong written, verbal and debugging skills
  • Knowledge of Communication protocols such as Ethernet MAC is a plus
  • Knowledge of bus communication protocol such as AXI


Job Posting: Feb 22, 2018, 7:04:12 PM

Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.


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San Jose, CA

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San Jose, CA

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